Self-alignment techniques for fabricating a-Si:H TFTs at 300C on clear plastic

We previously demonstrated highly stable backchannel cut and back-channel passivated amorphous silicon thin-film transistors (a-Si:H TFTs) made at 300C on 2.9-inch x 2.9-inch clear plastic substrates [1]. Mechanical stress in the TFT stack causes the substrate to expand or contract, which easily results in misalignment between consecutive device layers [2,3]. Therefore we developed three selfalignment processes to resolve this issue. To process (1) we self-aligned the channel passivation in back-channel passivated TFTs to the gate. To process (2) we self-aligned the source-drain terminals, and the a-Si:H island layer in backchannel cut TFTs to the gate. To process (3) we combined processes (1) and (2), which enabled us to fabricate backchannel passivated TFTs with the channel passivation, the source-drain terminals and the a-Si:H layer self-aligned to the gate. Using these processes we were able to reduce the TFT channel length to 5μm with a 1 μm source/drain (S/D) overlap, and obtained functional devices over the entire surface area of the plastic workpiece.